1. Field
The present invention relates generally to signal processing and, more particularly, to analog to digital conversion.
2. Description of Related Art
In many moderate bandwidth sigma-delta analog-to-digital converter (ADC) applications, flicker noise is a significant problem. Examples of such applications include audio and GSM which are economically significant markets. Flicker noise is noise that is characterized by a 1/f relationship such that lower frequencies tend to contribute more to the noise. This flicker noise problem is a significant issue with circuits fabricated with CMOS devices having a size of 45 nm and 65 nm.
In the past, some attempts have been made to reduce flicker noise and its effects. One approach has been to increase the devices sizes away from 45 nm. The result, however, is an ADC that is unattractively 2 to 4 times the size if flicker noise was not a problem. In addition to the unwanted size increase, parasitic capacitances also increase. To combat this, current consumption is necessarily increased to keep the parasitic poles from decreasing (it is known that low frequency parasitic poles cause instability within ADCs.)
Therefore, there remains, as yet an unfulfilled need for an ADC that reduces the impact of flicker noise but also provide a small device/circuit size and avoid impacting current and power consumption. One particular disadvantage of conventional chopping techniques is quantization noise folding, or aliasing, that can occur because of chopping at frequencies less than the ADC clock frequency. The lowest frequency at which chopping may be performed is determined, at least in part, by the flicker noise corner of the ADC. Different approaches to addressing this issue have been proposed. One technique may be to increase the number of quantization levels. However, this will also result in an increase in current and power consumption. Another technique would be to chop at a frequency above the Nyquist rate such as, for example fchop=fclk. However, this also results in increased power consumption and also the need for clock boosting circuits for the choppers in order to reduce switch resistance.